Contact:
Megan Moran
Aldec, Inc.
(702) 990-4400 ext. 201
meganm@aldec.com
FOR IMMEDIATE RELEASE
Free Web-Based VHDL & Verilog Tutorials
Henderson Nevada, October 17th, 2001-- Aldec, Inc., a leading supplier of HDL design entry and verification software for application specific integrated circuits (ASICs) and field programmable gate arrays (FPGAs), announced today that its VHDL and Verilog web-based tutorials are now available at no charge. Aldec's VHDL and Verilog tutorials were designed to educate traditional schematic and mixed-mode based users with the basic fundamentals for designing with HDLs. These tutorials help ease the learning curve and include a series of questions and answers to test system designers' knowledge of the language at the end of each chapter and comes with a complete VHDL or Verilog online reference manual with over 750 samples for using HDL constructs.
Aldec's HDL tutorials are of benefit to all designers because they focus on basic design structure and methodologies rather than training on a specific tool. There are two tutorials available to accommodate the broadest range of designers; the programs are positioned for either VHDL or Verilog languages and contain all of the information necessary to learn the essentials of each specific Hardware Description Language.
The tutorials follow the evolution of system design from Boolean equations to schematics to HDL designs, and how VHDL and Verilog languages can shorten the design cycle dramatically as compared to earlier design processes. The tutorials detail how HDL languages eliminate the need for manual translation of design description into a set of logical equations, consequently saving time and improving accuracy of the design.
Aldec recognizes that all designers can benefit from the interactive, vendor-independent tutorials. At the end of each interactive chapter, there is a brief question and answer section to help evaluate the effectiveness of the training and show which areas may want to be re-examined for further comprehension.
Availability
The HDL tutorials are available on Aldec's website, and may be accessed at any time. As part of its continuing effort to promote the latest in technology in the EDA industry, Aldec has made these tutorials available to customers free of charge.
About Aldec
Aldec, Inc. has offered PC and Workstation-based design entry and simulation solutions to FPGA and ASIC designers for more than 16 years. During this time, Aldec has signed several OEM agreements with IC vendors, such as Xilinx, Inc. (NASDAQ:XLNX) and Cypress Semiconductor Corp. (NYSE:CY). Aldec, headquartered in Henderson, Nevada, produces a universal suite of Windows, Linux and UNIX-based EDA tools that allow design engineers to implement their designs using several different design entry methods (Schematic Capture, State Machine, Block Diagram, VHDL, Verilog or ABEL). Aldec incorporates patented simulation technology and several design entry tools to provide a complete design entry and simulation solution. Founded in 1984, the company continues to evolve in the EDA market as the fastest growing verification company in the world. Additional information about Aldec is available at http://www.aldec.com.
Active-HDL is a trademark of Aldec, Inc. All other trademarks or registered
trademarks are property of their respective owners
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